Product Information

PRODUCT BROCHURE (PDF, 548 KB)

The Cswitch Configurable Switch Array.
Never before have so many resources been dedicated to your success.

Moving, storing and editing packets.

For a custom chip to deliver high performance in all types of networks, it has to move, store and edit packets at very high speeds. The Configurable Switch Array chip does just that. It’s the first configurable solution to deliver bandwidth at 40-100Gbps for a range of applications, making it capable of moving up to 6TBps of packets at speeds of up to 2 GHz. To handle editing tasks, the chip packs a rich assortment of Frame Header Parsers, Arithmetic Units, and RCAMs to edit and classify packets at 1 GHz speeds. For storing packets, the chip includes over 18Mb of on-chip memory, as well as support for the latest high speed memories, such as DDR2, RLDRAM2, and QDR2. All of these elements are, of course, completely configurable.

Configurability and reconfigurability.

Configurability has always come at a price, with the trade-offs in low gate density, inadequate performance, or high power. Not any more. With over 7 million equivalent ASIC gates, speeds of up to 100Gbps on chip, and the very latest in power management techniques, the Configurable Switch Array chip makes configurability worthwhile by making it uncompromisingly available.

Power efficiency built in.

For the very first time, the Configurable Switch Array Chip brings the considerable advantages of high performance at low power to all kinds of networking applications. Using the latest advancements in power management – some of which were invented by our design team – the chip automatically reduces power by shutting off clocks to sectors not in use, and allows designers to vary chip voltage to achieve the optimum total power requirements. This holistic approach to power-managed performance represents a substantial and welcome breakthrough for OEMs and customers alike.

High speed 2 GHz bus with innovative dataCrossconnect™ intersections.

Our 2 GHz, 20-bit wide bus runs in a grid above all the configurable resources on the surface of the Configurable Switch Array chip and provides up to 6 TBps of bandwidth to all of the major resource blocks. At each intersection, our innovative dataCrossconnect provides fast on- and off-ramps to speed packets back and forth between the resources, and ultimately, across and off the chip.