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Design Tools
Andara Development Tool Suite
The Andara Development Tool Suite is a fully automated RTL design automation tool for Cswitch’s high-performance Configurable Switch Array (CSA) devices. It fully supports an HDL design flow from capture and logic synthesis; through physical synthesis, placement, routing and timing analysis; and finally, to configuration bitstream generation.
Utilizing Magma Design Automation’s world-class synthesis and timing analysis technology, the Andara Development Tool Suite is the first development tool for configurable devices that supports ASIC-level signoff capabilities, putting the user in direct control of the design process.
To have a sign off capable design flow, a unified design environment is required to have the ability to work with both hierarchical architectures (including the ability to perform architecture-specific synthesis such as Boolean matching and LUT/multiplexer mapping) and high-end ASIC capabilities such as heterogeneous physical synthesis, placement, and static timing analysis.
Furthermore, the design environment needs to employ a single unified data model. This model, which must remain resident in memory to provide the high levels of performance required by large and complex designs, must contain all of the logical, timing, and physical data required by the implementation engines (optimization, placement, routing, etc.) and the static timing analysis engines.
| FLOW STEP |
DESCRIPTION |
SOFTWARE USED |
1 |
Design Capture |
Generate the requisite RTL, timing and placement constraints |
cs_macrogen, DCC Wizard |
| 2 |
RTL Synthesis |
Generate a timing optimized netlist mapped to CS90 primitives |
BlastCreateCswitch |
| 3 |
Placement |
Generate a timing optimized placement for the design |
BlastCreateCswitch |
| 4 |
Post-Placement |
Convert the placed volcano database to a Cswitch “db” file |
BlastCreateCswitch |
| 5 |
Routing |
Perform fabric and dataCrossconnect routing |
CSTOOL |
| 6 |
Timing Sign-Off |
Perform timing analysis on the fully-placed and routed netlist |
BlastCreateCswitch |
PacketParser Flow
The PacketParser CPEs make header parsing simple by allowing the use of C language to describe the parsing algorithm. Because of this capability, the PacketParser CPEs require additional steps in the design flow.
The PacketParser CPE design flow starts with a C language description of the parsing algorithm. This design file is then compiled using the ppc compiler and the ppa assembler, which are both provided with the Andara Productivity Utilities. The assembler generates an assembly language file representing the parsing algorithm, along with the instruction memory and data memory images.
Next, the resultant design can be verified using the pps simulator included in the Andara Productivity Utilities. Also at this stage, the number of PacketParser CPEs required in the ring is determined based upon the latency requirements of the system.
Once the PacketParser CPE ring configuration has been determined, cs_macrogen.py is used to create the instantiable module that contains the structural netlist describing the ring. It also calls out the instruction memory image and the data image that were generated by the ppa assembler. As with other CSA embedded blocks, an RTL simulation model is provided so verification in the RTL domain can be done.
Andara Development Tool Suite Features
Design Flow
- State-of-the-art graphical user interface with HDL, schematic, timing views, and cross probes
- Easy-to-use constraint management and editing
- Push-button automation, with support for Tcl scripting
- Unified data model enabling ASIC-class design sign off
RTL Synthesis
- Based on Magma Blast Create™ synthesis technology
- Standard VHDL/Verilog coding style
- Inferencing of Configurable Packet Engine (CPE) blocks (RAU, RCAM) and memories (SPRAM, DPRAM, ROM)
- Logic restructuring and cloning
- Architecture swapping during placement
Integrated Physical Synthesis and Placement
- Timing-driven optimizations including latency management for the dataCrossconnect
- Sequential optimizations (retiming)
- Constraint-driven placement and mapping
Comprehensive Static Timing Analysis
- Based on Magma QuartzTimeTM static analysis technology
- Hierarchical timing constraints
- Pre- and post-route static timing analysis and views
- Layout editor
- Back annotation
Open Access Architecture Supports 3rd-Party Tool Flows
- Input: Verilog, System Verilog, VHDL, SDC, .mtcl
- Output: Verilog, SDC, SDF
- Tcl-based scripting supported
Includes the Andara Productivity Utilities
- Router
- Programming file generator
- PacketParser CPE utilities: C compiler, assembler, and simulator
- GeXp graphical physical viewer
- Macro generator supporting the instantiation of MACs, memories, FIFOs, and CRC blocks
- A library of common networking functions optimized for the Configurable Switch Array architecture
Platform Requirements
- Centos 4.5, RedHat Enterprise 4 Linux OS or equivalent
- 2GHz processor with 2GB RAM
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