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Devices
CS90 Configurable Switch Array Family
Based upon the Configurable Switch Array (CSA) architecture, the CS90 family breaks through the efficiency and performance issues associated with FPGAs, and the flexibility and cost of ownership issues associated with ASICs. A purpose-built interconnect structure eliminates data path bottlenecks caused by segmented wires; and configurable logic structures specifically designed to support packet-oriented functions provide the best area and power efficiency per function available today. Memory needs are addressed with memory blocks tailored for shift registers, buffers, and tables, as well as embedded high-speed controllers supporting the fastest memories available today. High-speed serial and parallel interface protocols such as XAUI, Fibre Channel, PCI-Express, SPI-4.2, and others are flexibly supported with single-ended, differential, and serial I/O. These elements come together to offer ASIC-like performance and logic efficiency, while still maintaining FPGA-like flexibility.
The Configurable Switch Array (CSA) architecture is well suited to meet a variety of performance and logic requirements. The CSA architecture is fundamentally column based, and serves as a scalable platform for the CS90 family. By leveraging this capability, the CS90 family spans a broad range of applications, from port aggregation to traffic management to deep packet inspection to queue management and general switch fabric interface.
The CS90 Configurable Switch Array offers the following features:
- Two levels of interconnect for maximum bandwidth and flexibility
- The dataCrossconnect network, a high-performance dedicated interconnect network for fast communication between blocks at speeds up to 2-GHz
- A logic fabric interconnect, providing maximum flexibility for general purpose routing
- Configurable Packet Engine (CPE) Tiles designed to efficiently handle packet operations:
- Microcode based PacketParser blocks for parsing of packets at up to 800 MIPS
- Reconfigurable CAM (RCAM) blocks for either binary, ternary, or byte-wise lookup, ideal for packet classification applications at speeds up to 1-GHz
- Reconfigurable Arithmetic Unit (RAU) blocks optimized for packet arithmetic such as CRC calculations, hashing, and Galois field mathematics, as well as DSP functions at speeds up to 1-GHz
- Memory Tiles with up to 18,400 Kb of 1-GHz embedded memory with built-in FIFO support
- Dual-Port RAM: Up to 120 true dual-port 20 Kb RAM/FIFO blocks
- Single-Port RAM: Up to 10 1280 Kb and 5 640 Kb single-port RAM/FIFO blocks, with block partition support
- Up to 608 Kb of additional memory space available from RCAM blocks and Programmable Logic Blocks, giving a total memory space of 19,008 Kb:
- Up to 64 single-port 64x40 RAM available from RCAM block
- Up to 7,168 Local RAM blocks (16x4 LRAM) included in Programmable Logic Blocks
- Interface Tiles for on/off chip communications:
- Up to six Quad MAC/PCS/SERDES (MPS) blocks, which includes:
- Four MACs that can be configured as 10/100/1000 Mbps Ethernet or 1G/2G/4G Fibre Channel, for a total of 24 MACs
- A 10G Ethernet MAC, for a total of 6 MACs
- PCS block compatible with 10/100/1000 Mbps Ethernet, SGMII, XAUI, Fibre Channel, plus 8B/10B encoding for user defined protocols
- Memory Controller embedded blocks to perform address and control operations for external memory devices
- Support for DDR (200 MHz), DDR2 (533 MHz), QDR (166 MHz), QDR II (300 MHz), RLDRAM (200 MHz), and RLDRAM II (533 MHz)
- Up to four Memory Controllers
- Flexible I/Os for high-speed interfaces:
- Single-ended data rates of up to 1067 Mbps
- Differential data rates of up to 1000 Mbps
- Supported I/O Standards: LDT, LVDS, GTLP, HSTL I / II / III (1.5V), LVCMOS (1.5V, 1.8V, 2.5V), SSTL I / II (1.8V, 2.5V)
- Process, Voltage and Temperature compensated on-chip termination option
- Built-in SDR/DDR registers, FIFOs, Delay Locked Loop (DLL) and Error Correction Code (ECC) logic for use with memory interface solutions and networking interfaces standards such as SPI-4.2, and XSBI
- Up to 640 user I/O pins distributed across 16 I/O banks
- Up to 24 high speed serial transceivers configurable to operate from 1.06 to 6.4 Gbps
- Serial electrical standards supported: CEI 6G, XAUI, PCI-Express, and Serial ATA
- Flexible, robust clocking structures
- Up to 16 buffered global clock trees with glitchless switchover circuit for speed up to 2-GHz
- Local clock buffers distributed across the chip with clock dividers to support a high number of clock subdomains
- Up to 4 I/O receive clock domains per I/O bank designed for source-synchronous data capture applications
- Up to 8 Phased Locked Loops (PLLs) with output clocks up to 2-GHz with frequency synthesis, clock de-skew, and input jitter filtering support
- Up to 7,168 Programmable Logic Blocks (PLBs), equivalent to 57,344 Logic Elements, for custom logic functions. Each PLB consists of:
- 8 four-input LUTs
- 4 fully-configurable registers
- 1 Local RAM block (16x4) also configurable into four registers
- Dedicated carry lookahead chain logic
- A variety of device configuration options:
- Master Serial
- Slave Serial
- Slave 8-bit Parallel
- JTAG
- 128-bit AES bitstream encryption for design security
- Flip-chip high-density build-up package with I/O:GND:PWR ratio of 6:1:1, along with on-die and on-package decoupling for robust signal integrity
- Built on 90-nm CMOS process technology
- 1.2V core voltage
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