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Memory Interfaces
The CS90 family includes embedded blocks to address your on-chip and off-chip memory needs. With up to 18Mbits of embedded memory, running at a clock speed of up to 1GHz, the CS90 family offers the largest and fastest embedded memory blocks at various capacities, with programmable port widths and built-in FIFO logic. The CS90 family simplifies your external memory requirement by using the built-in Memory Controller embedded blocks. Each Memory Controller block can address up to 4 Gbytes of external memory at a data rate of over 1Gbps.
Single-Port RAM
With a clock speed of up to 1GHz, the Single-Port RAMs are the largest memory blocks available in the CS90 family of devices. Two sizes are available in the CS90 family of devices: 640 Kb or 1280 Kb RAM. These memory blocks are suited for on-chip memory buffering and storage of your application’s data. The depth and width are configurable from 16Kx80 to 128Kx10. In addition, an optional partitioning into 1, 2, or 5 independent SPRAM blocks is available in these memory blocks. The block partitioning capability allows packing of smaller memory size into one single port RAM block for resource conservation.
The SPRAM can also be configured as a Pseudo-dual-port RAM with speeds up to 500 MHz. An Optional FIFO mode is also available with Full and Empty flag support, configurable NEAR_FULL and NEAR_EMPTY flags, synchronous/asynchronous operation, and speculative pushes and pops with rollback to a prior committed state support at speeds of up to 500 MHz.
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Note: 640Kb SPRAMs are ½ Depth |
Dual-Port RAM
The true Dual-Port 20 Kb RAMs, with optional output registers, are suitable for applications that require simultaneous memory access. Running at a clock speed of up to 1GHz, the Dual-Port RAM’s depth and width is configurable from 512×40 to 16K×1. Optional FIFO mode support is available with Full and Empty flags, configurable NEAR_FULL and NEAR_EMPTY flags, synchronous/asynchronous operation, and speculative pushes and pops with rollback to a prior committed state support.
Local RAM
Each Programmable Logic Block (PLB) contains one 16x4 Local RAM. This memory block is separate from the Look Up Tables (LUTs) resources of the PLB, and suitable for localized memory storage or mini-memory applications. Up to 7,168 Local RAMs are available in select CS90 devices.
Reconfigurable CAM (RCAM) as SRAM
Should your networking applications need more memory, the Reconfigurable CAM can be configured into a Single-Port 64x40 RAM, running at a clock speed of up to 1GHz.
THE FASTEST EXTERNAL MEMORY SOLUTION:
The CS90 family simplifies external memory requirements for your networking applications. Every device of the CS90 the family includes built-in Memory Controller embedded blocks. The Memory Controller block, in conjunction with the General Purpose I/Os (GPIOs), provides a complete high-performance solution for interfacing with popular external memory devices. Up to 4 Memory Controller blocks are available in the CS90 device. Each Memory Controller block can address up to 4 Gbytes of external memory, providing a total memory handling capability of 16 Gbytes for a select CS90 device.
Memory Controller Block
The Memory Controller block simplifies your external memory requirements by providing complete addressing and control functions for the supported memory standards.
The Memory Controller block translates all the read/write requests into the protocol appropriate signals for the supported memory standard in use. The logic automatically remaps the address space into rows, columns, and banks for all supported memories. The logic monitors all signals from the user interface, schedules commands to the supported external memory, and manages timing relationships as required by the various supported memory devices.
An address FIFO is provided to allow queues of read and write requests to external memory. It can also be used for burst access to external memory, starting at a given address. The FIFO is designed to allow a maximum access of 511 bursts.
The Memory Controller block also has 64 individual configuration registers. These registers provide a dedicated interface with custom logic implemented in the PLB resources. These registers also handle information about mode register settings, address and data widths, memory types, timing parameters, and other operational features of the Memory Controller block.
Other Features
Other features of the Memory Controller block include:
- Flexible memory address mapping and length field to allow memory bursts improved performance and a reduction in the number of dead cycles
- Memory command overlapping to increase the efficiency of data transfer between custom logic and external memory
- Read/modify/write operations for partial word write into external memory
- Configurable data widths of 8 to 72
- Power management of external memory
Dedicated connections to the General Purpose I/Os allow the Memory Controller block to use certain functions of the General Purpose I/Os for implementation of the datapath between user logic and external memory.
The General Purpose I/O datapath logic routes data, checks and corrects data errors using the built-in ECC, and provides SDR-to-DDR and DDR-to-SDR conversion. The configurable I/O standards and on-chip termination of the General Purpose I/Os provide the analog interface for your external memory requirements.
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