Networking Interfaces

The CS90 family of Configurable Switch Array (CSA) devices is designed to be the most power- and area- efficient chips for implementing multiple 1G and 10G Ethernet solutions. The CS90 family contains up to twenty-four 1G and six 10G Ethernet MACs that require no Programmable Logic Blocks (PLBs) to implement a complete solution. In contrast, FPGAs that utilize soft IP based Ethernet MACs can require a significant number of LUTs and Flip Flops resources (see charts below). In some of the larger 90nm FPGA devices, the soft IP can consume more than half the available resources.

In addition to saving PLBs, the CS90 family offers a fast interconnection from the 1GbE and 10GbE to any on chip or off-chip resource through the dataCrossconnect bus. Operating at up to 2Ghz, the 20 bit wide parallel bus can deliver up to 40Gbps of data between any chip resources.

Lowest Power Ethernet Solutions

Cswitch’s CS90 family, with its integrated MACs, is much more power efficient than 90nm FPGAs built with soft IP MACs or 65nm FPGAs that include a combination of embedded MACs and soft IP based MACs.

The chart below shows a 2.6 to 4.8 advantage in dynamic power. In regard to static power, the CS90 is better than 90nm FPGAs and similar to 65nm FPGAs.

MAC Feature Set

• Configurable as one of the following
  • 10G Ethernet
  • 1G/100M/10M Ethernet
  • 1/2/4G Fibre Channel link control
  • Bypass mode (Customer can implement proprietary/other MAC protocols in Cswitch PLB - programmable fabric)
    
    
• Standard Support
  • IEEE 802.3ae standard compliant in 10G Ethernet mode
  • IEEE 802.3 MAC compliance for 10/100/1000 Mbps Ethernet mode
  • IEEE 802.3x full duplex flow control for 1G/10G Ethernet
  • FC_PH for Fiber Channel link control
    
    
• Features in all MAC Modes
  • Programmable endian byte swapping
  • Programmable FIFO for clock domain synchronization between network and systems clocks
  • Programmable padding to minimum frame size
  • Support for externally generated proprietary control frames
  • Programmable FCS insertion on transmit
    
    
• Ethernet MAC Features
  • Full duplex flow control (802.3x)
  • Programmable VLAN aware/ignore padding
  • Programmable minimum average IPG
  • IPG dithering for minimum IPG maintenance
  • Supports transmission/reception of odd byte frames
  • Programmable MAC address
  • 51 transmit and 31 receive RMON & SNMP statistics
  • Programmable modulus adjustment for SONET OC-192 data rate control tuning for 10G MAC
    
    
• 1/2/4G Fibre Channel Link Control Features
  • Support for proprietary headers
  • Programmable IPG
  • Programmable SOF and EOF delimiter insertion/removal
  • Support for flow control and buffer credit management
  • Programmable FCS calculation start point
  • Supports transmission of local and remote faults sequences manually or automatically
  • Supports detection of local and remote faults
  • Transceiver management through MII Interface
  • Separate Host Interface for control/status transfer
    

Quad MAC/PCS/SERDES Block

The Quad MAC/PCS/SERDES (MPS) block provides four full-duplex channels of up to 6.4Gpbs serial transceivers for the CS90 family of devices. In addition, four built-in MAC and PCS layer logic blocks, compatible to popular standards such as 10/100/1000 Ethernet, Fibre Channel, and 10G Ethernet, are included for implementation of complete high-speed networking solutions.

A parallel data interface and built-in serializer/deserializer (SERDES) are included for interfacing between the transceiver blocks and the other logic blocks within the CS90 family of devices. The parallel interface data widths are for 8-bit, 10-bit, 16-bit, or 20-bit parallel data, running at speeds of up to 320-MHz. In addition, each channel contains BIST circuitry with PRBS and 8B/10B patterns and loop back modes for debugging purposes.

Within a Quad MPS block, all four channels share a control block. The shared block generates all required bias currents, contains startup and calibration logic, and contains the PLL which multiplies the reference clock to the required serial link rate; providing the reference clock for each of the Clock/Data Recovery (CDR) units. An integrated band gap and PLL voltage regulator is implemented for superior jitter performance. A built-in impedance calibrator allows automatic calibration of the transmitter and receiver termination resistances against process, temperature, and voltage variations by calibrating internal resistances against an external, precision resistance.

One of the four MAC blocks contains logic to support the 10G Ethernet protocol, along with an MDIO interface. This specific MAC can be used with all four channels to create a XAUI based 10G Ethernet solution. In addition, the MAC Bypass mode is also available to create other MAC protocols such as SONET, PCIExpress, or custom protocols using the PLB resources.

There are also four built-in PCS blocks in the Quad MPS block. The PCS is designed to support 10/100/1000 Ethernet, Fibre Channel, SGMII, and XAUI for 10G Ethernet support. The PCS supports these protocols using the following features:

• 8B/10B Encoder and Decoder
• TX/RX FIFOs for clock domain crossing
• User programmable 10-bit comma detect and word alignment (default to K28.5)
• Bypass Mode for PLB-resource-based custom protocol solution
• Lane alignment for XAUI
• Loopbacks for debugging
• Application specific functional features:
  • Gigabit Ethernet state machine (IEEE 802.3 compliant)
  • XAUI state machine (IEEE 802.3ae compliant)
  • Rate Adaptation (SGMII version 1.7)
  • Auto Negotiation (SGMII version 1.7)
  • PCI-express
    

Table 3 Quad MPS Supported Protocols

Related Links

• CS90 MPS User Guide (PDF, 3.1 MB)

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